K60P100M100SF2RM Datasheet, PDF (1257/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 45 Universal Serial Bus OTG Controller (USBOTG)
45.4.14 Control Register (USBx_CTL)
The Control Register provides various control and configuration information for the USB
Module.
Addresses: USB0_CTL is 4007_2000h base + 94h offset = 4007_2094h
Bit
7
6
5
4
3
2
1
0
Read
JSTATE
SE0
Write
RESET
RESUME ODDRST
Reset
0
0
0
0
0
0
0
0
USBx_CTL field descriptions
Field
Description
7
JSTATE
Live USB differential receiver JSTATE signal
The polarity of this signal is affected by the current state of LSEN .
6
Live USB Single Ended Zero signal
SE0
5
When the USB Module is in Host mode TOKEN_BUSY is set when the USB Module is busy
TXSUSPENDTOKENBUSY executing a USB token and no more token commands should be written to the Token Register.
Software should check this bit before writing any tokens to the Token Register to ensure that
token commands are not lost. In Target mode TXD_SUSPEND is set when the SIE has
disabled packet transmission and reception. Clearing this bit allows the SIE to continue token
processing. This bit is set by the SIE when a Setup Token is received allowing software to
dequeue any pending packet transactions in the BDT before resuming token processing.
4
RESET
Setting this bit enables the USB Module to generate USB reset signaling. This allows the USB
Module to reset USB peripherals. This control signal is only valid in Host mode
(HOSTMODEEN=1). Software must set RESET to 1 for the required amount of time and then
clear it to 0 to end reset signaling. For more information on RESET signaling see Section
7.1.4.3 of the USB specification version 1.0.
3
HOSTMODEEN
When set to 1, this bit enables the USB Module to operate in Host mode. In host mode, the
USB module performs USB transactions under the programmed control of the host processor.
2
RESUME
When set to 1 this bit enables the USB Module to execute resume signaling. This allows the
USB Module to perform remote wake-up. Software must set RESUME to 1 for the required
amount of time and then clear it to 0. If the HOSTMODEEN bit is set, the USB module
appends a Low Speed End of Packet to the Resume signaling when the RESUME bit is
cleared. For more information on RESUME signaling see Section 7.1.4.5 of the USB
specification version 1.0.
1
ODDRST
Setting this bit to 1 resets all the BDT ODD ping/pong bits to 0, which then specifies the EVEN
BDT bank.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1257