K60P100M100SF2RM Datasheet, PDF (123/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Wait
Normal Stop
Low Power Stop
Table 3-47. ADC low-power modes
Chapter 3 Chip Configuration
Module mode
Chip mode
Wait, VLPW
Stop, VLPS
LLS, VLLS3, VLLS2, VLLS1
3.7.1.11 PGA Integration
• No additional external pins are required for the PGA as it is part of the ADC and is
selected as a separate channel
• Each PGA connects to the differential ADC channels
• The PGA outputs differential pairs that are connected to ADC differential input
• When the PGA is used, differential input from the pins is connected to differential
input channel 2 on ADCx
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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