K60P100M100SF2RM Datasheet, PDF (448/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
Absolute
address
(hex)
DMA memory map (continued)
Register name
Width
(in bits)
Access
Reset value
4000_91F6 DMA_TCD15_CITER_ELINKNO
16
R/W Undefined
4000_91F8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD15_DLASTSGA)
32
R/W Undefined
4000_91FC TCD Control and Status (DMA_TCD15_CSR)
16
R/W Undefined
TCD Beginning Minor Loop Link, Major Loop Count
4000_91FE (Channel Linking Enabled)
(DMA_TCD15_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
4000_91FE (Channel Linking Disabled)
(DMA_TCD15_BITER_ELINKNO)
16
R/W Undefined
16
R/W Undefined
Section/
page
21.3.27/
478
21.3.28/
479
21.3.29/
480
21.3.30/
482
21.3.31/
483
21.3.1 Control Register (DMA_CR)
The CR defines the basic operating configuration of the DMA.
Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For
fixed-priority arbitration, the highest priority channel requesting service is selected to
execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
For round-robin arbitration, the channel priorities are ignored and channels are cycled
through without regard to priority.
NOTE
For proper operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
Address: DMA_CR is 4000_8000h base + 0h offset = 4000_8000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
0
0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CR field descriptions
Field
31–18
Reserved
17
CX
Description
This read-only field is reserved and always has the value zero.
Cancel Transfer
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
448
Freescale Semiconductor, Inc.