K60P100M100SF2RM Datasheet, PDF (71/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
Bus name
Description
Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is
Data code (DCODE) bus
connected to the crossbar switch via a single master port. In addition, the CODE bus is also
tightly coupled to the lower half of the system RAM (SRAM_L).
System bus
The system bus is connected to a separate master port on the crossbar. In addition, the
system bus is tightly coupled to the upper half system RAM (SRAM_U).
Private peripheral (PPB) bus
The PPB provides access to these modules:
• ARM modules such as the NVIC, ETM, ITM, DWT, FBP, and ROM table
• Freescale Miscellaneous Control Module (MCM)
• Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
3.2.1.2 System Tick Timer
The System Tick Timer's clock source is always the core clock, FCLK. This results in the
following:
• The CLKSOURCE bit in SysTick Control and Status register is always set to select
the core clock.
• Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the
SysTick Calibration Value Register is always zero.
• The NOREF bit in SysTick Calibration Value Register is always set, implying that
FCLK is the only available source of reference timing.
3.2.1.3 Debug facilities
This device has extensive debug capabilities including run control and tracing
capabilities. The standard ARM debug port that supports JTAG and SWD interfaces.
Also the cJTAG interface is supported on this device.
3.2.1.4 Core privilege levels
The ARM documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term...
Privileged
Unprivileged or user
it also means this term...
Supervisor
User
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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