K60P100M100SF2RM Datasheet, PDF (159/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
3.9.8.1 Interrupts
The interrupt outputs from the I²S module are OR'd to create a single interrupt to the
interrupt control logic.
3.9.8.2 DMA requests
The I²S module has two DMA requests:
• Transmit FIFO
• Receive FIFO
3.9.8.3 I²S clock generation
To generate the desired frequencies for the I²S module there are multiple clocking
options as shown below:
• The core/system clock is routed to an 8-bit fractional divider to generate the I²S
clock.
• The PLL output is routed to an 8-bit fractional divider to generate the I²S clock.
• The EXTAL pin directly drives the I²S clock.
• The I2S0_CLKIN pin directly drives the I²S clock.
These options are controlled by the SIM_SOPT2[I2SSRC] field, and the 8-bit fractional
divider is controlled by the SIM_CLKDIV2[I2SDIV, I2SFRAC] fields. See the SIM
module for details.
3.9.8.4 I²S operation in low power modes
The I²S module requires interaction with the rest of the system to move data in or out of
the FIFOs. Since the rest of the system is not active in stop, VLPS, and LLS modes, there
is no use for the I²S in these modes. The I²S is powered so that it retains state in these
modes, but it is not functional.
In VLPR and VLPW modes, the I²S is functional. However, the I²S is limited to 400 kHz
maximum frequency.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
159