K60P100M100SF2RM Datasheet, PDF (227/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 9 Debug
9.11 Coresight Embedded Trace Buffer (ETB)
The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts
trace data from any CoreSight-compliant component trace source with an ATB master
port, such as a trace source or a trace funnel. It is included in this device to remove
dependencies from the trace pin pad speed, and enable low cost trace solutions. The
TraceRAM size is 2 KB.
ATB slave port
ATB
i/f
Formatter
TRIGIN
(from ETM Trigger out)
Control
Trace RAM
interface
APB
APB
i/f
Register Bank
TraceRAM
Figure 9-4. ETB Block Diagram
The ETB contains the following blocks:
• Formatter -- Inserts source ID signals into the data packet stream so that trace data
can be re-associated with its trace source after the data is read back out of the ETB.
• Control -- Control registers for trace capture and flushing.
• APB interface -- Read, write, and data pointers provide access to ETB registers. In
addition, the APB interface supports wait states through the use of a PREADYDBG
signal output by the ETB. The APB interface is synchronous to the ATB domain.
• Register bank -- Contains the management, control, and status registers for triggers,
flushing behavior, and external control.
• Trace RAM interface -- Controls reads and writes to the Trace RAM.
9.11.1 Performance Profiling with the ETB
To create a performance profile (e.g. gprof) for the target application, a means to collect
trace over a long period of time is needed. The ETB buffer is too small to capture a
meaningful profile in just one take. What is needed is to collect and concatenate data
from the ETB buffer for multiple sequential runs. Using the ETB packet counter
(described in Miscellaneous Control Module (MCM)), the trace analysis tool can capture
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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