K60P100M100SF2RM Datasheet, PDF (1732/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
• Tx frame sync initiated one bit before data is transmitted (TCR[TEFS] = 1)
• Rx frame sync initiated one bit before data is received (RCR[REFS] = 1)
• Tx shifting w.r.t. bit 0 of TXSR (TCR[TXBIT0] = 1)
• Rx shifting w.r.t. bit 0 of RXSR (RCR[RXBIT0] = 1)
• Tx FIFO is enabled (TCR[TFEN0] = 1)
• Rx FIFO is enabled (RCR[RFEN0] = 1)
• Internally-generated frame sync (TCR[TFDIR] = 1)
• Externally-generated bit clock (TCR[TXDIR] = 0)
Any alteration of these bits does not affect the operational conditions of the I²S unless
AC97 mode is deselected. Hence, the only control bits that need to be set to configure the
data transmission/reception are the TCCR[WL, DC] bits. In AC97 mode, the WL bits can
only legally take the values corresponding to 16-bit (truncated data) or 20-bit time slots.
If the WL bits are set to select 16-bit time slots while receiving, the I²S pads the transmit
data (four least significant bits) with zeros and while receiving, the I²S stores only the 16
most significant bits in the Rx FIFO.
Follow the sequence for programming the I²S to work in AC97 mode:
1. Program the TCCR[WL] bits to a value corresponding to 16 or 20 bits. The WL bit
setting is only for the data portion of the AC97 frame (slots #3 through #12). The tag
slot (slot #0) is always 16 bits wide and the command address and command data
slots (slots #1 and #2) are always 20 bits wide.
2. Select the number of time slots through the TCCR[DC] bits. For AC97 operation, the
DC bits should be set to a value of 0xC, resulting in 13 time slots per frame.
3. Write data to be transmitted in Tx FIFO 0 (through Tx data register 0) and Tx FIFO 1
while using two-channel mode (CR[TCHEN] = 1).
4. Program the ACNT[FV, TIF, RD, WR, and FRDIV] bits
5. Update the contents of ACADD, ACDAT, and ATAG (for fixed mode only) registers
6. Enable AC97 mode (ACNT[AC97EN])
After the I²S starts transmitting and receiving data (after being configured in AC97
mode), the processor needs to service the interrupts when they are raised (updates to
command address/data or tag registers, reading of received data, and writing more data
for transmission). Further details regarding fixed and variable mode implementation
appear in the following sections.
1732
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.