K60P100M100SF2RM Datasheet, PDF (1583/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
31–0
CMDRSP3
Chapter 52 Secured digital host controller (SDHC)
SDHC_CMDRSP3 field descriptions
Command Response 3
Description
52.4.9 Buffer Data Port Register (SDHC_DATPORT)
This is a 32-bit data port register used to access the internal buffer and it can not be
updated in idle mode.
Address: SDHC_DATPORT is 400B_1000h base + 20h offset = 400B_1020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATCONT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_DATPORT field descriptions
Field
31–0
DATCONT
Data Content
Description
The Buffer Data Port register is for 32-bit data access by the CPU or the external DMA. When the internal
DMA is enabled, any write to this register is ignored, and any read from this register will always yield 0s.
52.4.10 Present State Register (SDHC_PRSSTAT)
The host driver can get status of the SDHC from this 32-bit read only register.
NOTE
The host driver can issue CMD0, CMD12, CMD13 (for
memory) and CMD52 (for SDIO) when the DAT lines are busy
during a data transfer. These commands can be issued when
Command Inhibit (CIHB) is set to zero. Other commands shall
be issued when Command Inhibit (CDIHB) is set to zero.
Possible changes to the SD Physical Specification may add
other commands to this list in the future.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1583