K60P100M100SF2RM Datasheet, PDF (201/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 6 Reset and Boot
4. The RESET pin is released, but the system reset of internal logic continues to be held
until the Flash Controller finishes initialization. EzPort mode is selected instead of
the normal CPU execution if EZP_CS is low when the internal reset is deasserted.
EzPort mode can be disabled by programming FTFL_FOPT[EZPORT_DIS]. Note: If
recovering from VLLS1, 2, or 3 with the LLWU_P3 wakeup pin (PTA4/
FTM0_CH1/NMI/EZP_CS), use rising-edge wakeup in the LLWU or disable EzPort
mode to ensure normal recovery.
5. When Flash Initialization completes, the RESET pin is observed. If RESET
continues to be asserted (an indication of a slow rise time on the RESET pin or
external drive in low), the system continues to be held in reset. Once the RESET pin
is detected high, the system is released from reset.
6. At release of system reset, clocking is switched to a slow clock if
FTFL_FOPT[LPBOOT] is configured for Low Power Boot
7. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table
offset 0. The core reads the start PC from vector-table offset 4. LR is set to
0xFFFF_FFFF. The CPU begins execution at the PC location. EzPort mode is
entered instead of the normal CPU execution if Ezport mode was latched during the
sequence.
8. If FlexNVM is enabled, the flash controller continues to restore the FlexNVM data.
This data is not available immediately out of reset and the system should not access
this data until the flash controller completes this initialization step as indicated by the
EEERDY flag.
Subsequent system resets follow this reset flow beginning with the step where system
clocks are enabled.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
201