K60P100M100SF2RM Datasheet, PDF (1018/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
If (SYNCMODE = 0), (SYNCHOM = 1) and (PWMSYNC = 0) then this
synchronization is done on the next enabled trigger event. If the trigger event was a
software trigger then the SWSYNC bit is cleared on the next selected loading point. If the
trigger event was a hardware trigger then the TRIGn bit is cleared according to Hardware
Trigger. Examples with software and hardware triggers follow.
system clock
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
selected loading point
OUTMASK register is updated SWSYNC bit is cleared
Figure 39-215. OUTMASK Synchronization with (SYNCMODE = 0), (SYNCHOM = 1),
(PWMSYNC = 0) and (Software Trigger Was Used)
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
OUTMASK register is updated and
TRIG0 bit is cleared
Figure 39-216. OUTMASK Synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(SYNCHOM = 1), (PWMSYNC = 0), and (a Hardware Trigger Was Used)
If (SYNCMODE = 0), (SYNCHOM = 1) and (PWMSYNC = 1) then this
synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared
according to Hardware Trigger. An example with a hardware trigger follows.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.