K60P100M100SF2RM Datasheet, PDF (1477/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
• Receiver data buffer overrun
• Receiver data buffer underflow
• Transmit data buffer overflow
• Noise error
• Framing error
• Parity error
• Active edge on receive pin
• LIN break detect
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
• DMA interface
51.1.2 Modes of operation
The UART functions the same in all the normal modes.
It has two low power modes: Wait and Stop modes.
51.1.2.1 Run mode
This is the normal mode of operation.
51.1.2.2 Wait mode
UART operation in wait mode depends on the state of the C1[UARTSWAI] bit.
• If the C1[UARTSWAI] bit is cleared, the UART operates normally when the CPU is
in Wait mode.
• If the C1[UARTSWAI] bit is set, UART clock generation ceases and the UART
module enters a power-conservation state when the CPU is in Wait mode.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1477