K60P100M100SF2RM Datasheet, PDF (1390/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
eDMA
INTC
Slave Bus Interface
Clock/Reset
SPI
DMA and Interrupt Control
PUSHR
POPR
CMD Data
Data
32
32
Shift Register
S PI
Baud Rate, Delay &
Transfer Control
8
Figure 49-1. DSPI Block Diagram
SOUT
SIN
SCK
PCS[x]/SS/PCSS
49.1.2 Features
The DSPI supports these SPI features:
• Full-duplex, Four-wire synchronous transfers
• Master and slave modes
• Data streaming operation in slave mode with continuous slave selection
• Buffered transmit operation using the TX FIFO with depth of 4 entries
• Buffered receive operation using the RX FIFO with depth of 4 entries
• TX and RX FIFOs can be disabled individually for low-latency updates to SPI
queues
• Visibility into TX and RX FIFOs for ease of debugging
• Programmable transfer attributes on a per-frame basis:
1390
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.