K60P100M100SF2RM Datasheet, PDF (1132/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

External Signal Description
MII
MII_MDIO
MII_RXCLK
MII_RXDV
MII_RXD[3:0]
MII_RXER
MII_TXCLK
MII_TXD[3:0]
MII_TXEN
MII_TXER
—
RMII
RMII_MDIO
—
RMII_CRS_DV
Description
I/O
Transfers control information I/O
between the external PHY
and the media-access
controller. Data is
synchronous to MDC. This
signal is an input after reset.
In MII mode, provides a
I
timing reference for RXDV,
RXD[3:0], and RXER.
Asserting this input indicates I
the PHY has valid nibbles
present on the MII. RXDV
must remain asserted from
the first recovered nibble of
the frame through to the last
nibble. Asserting RXDV must
start no later than the SFD
and exclude any EOF.
RMII_RXD[1:0]
RMII_RXER
—
RMII_TXD[1:0]
RMII_TXEN
—
RMII_REF_CLK
In RMII mode, this pin also
generates the CRS signal.
Contains the Ethernet input I
data transferred from the
PHY to the media-access
controller when RXDV is
asserted.
When asserted with RXDV, I
indicates the PHY detects an
error in the current frame.
Input clock which provides a I
timing reference for TXEN,
TXD[3:0], and TXER.
The serial output Ethernet
O
data and only valid during the
assertion of TXEN.
Indicates when valid nibbles O
are present on the MII. This
signal is asserted with the
first nibble of a preamble and
is negated before the first
TXCLK following the final
nibble of the frame.
When asserted for one or
O
more clock cycles while
TXEN is also asserted, PHY
sends one or more illegal
symbols.
In RMII mode, this signal is I
the reference clock for
receive, transmit, and the
control interface.
Table continues on the next page...
1132
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.