K60P100M100SF2RM Datasheet, PDF (1770/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
TSIx_SCANC field descriptions (continued)
Field
5
AMCLKDIV
4–3
AMCLKS
2–0
AMPSC
Active mode clock divider
0 Divider set to 1
1 Divider set to 2048
Active mode clock source
00 Bus Clock
01 MCGIRCLK
10 OSCERCLK
11 Not valid
Active mode prescaler
000 Input clock source divided by 1
001 Input clock source divided by 2
010 Input clock source divided by 4
011 Input clock source divided by 8
100 Input clock source divided by 16
101 Input clock source divided by 32
110 Input clock source divided by 64
111 Input clock source divided by 128
Description
55.6.3 Pin enable register (TSIx_PEN)
NOTE
Do not change PEN when GENCS[TSIEN] is set.
NOTE
All PEN bits can be read at any time, but must not be written
while GENCS[SCNIP] is set.
Addresses: TSI0_PEN is 4004_5000h base + 8h offset = 4004_5008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
LPSP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSIx_PEN field descriptions
Field
31–20
Reserved
19–16
LPSP
Description
This read-only field is reserved and always has the value zero.
Low-power scan pin
Table continues on the next page...
1770
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.