K60P100M100SF2RM Datasheet, PDF (180/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Clock definitions
Muliplexers
Dividers
Clock gates
OSC
MCG_Cx
—
OSC_CR
MCG
MCG_Cx
MCG_Cx
MCG_C1
SIM
SIM_SOPT1, SIM_SOPT2
SIM_CLKDIVx
SIM_SCGCx
EXTAL
XTAL
EXTAL32
XTAL32
MCG
SIM
4 MHz IRC ^÷2
CG
32 kHz IRC
÷2
MCGIRCLK
MCGFFCLK
Clock options for
some peripherals
(see note)
FLL
PLL
FRDIV
System oscillator
OSC
logic
OSCCLK
XTAL_CLK
CG
OSC32KCLK
OUTDIV1
CG
MCGOUTCLK
OUTDIV2
CG
OUTDIV3
CG
MCGFLLCLK
MCGPLLCLK
OUTDIV4
CG
MCGPLLCLK/
MCGFLLCLK
Core / system clocks
Bus clock
FlexBus clock
Flash clock
OSCERCLK
ERCLK32K
RTC oscillator
OSC logic
PMC
PMC logic
LPO
Real-time clock
CG — Clock gate
Note: See subsequent sections for details on where these clocks are used.
Figure 5-1. Clocking diagram
5.4 Clock definitions
The following table describes the clocks in the previous block diagram.
Clock name
Core clock
System clock
Description
MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex-
M4 core
MCGOUTCLK divided by OUTDIV1 clocks the crossbar
switch and bus masters directly connected to the crossbar. In
addition, this clock is used for UART0 and UART1.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
180
Freescale Semiconductor, Inc.