K60P100M100SF2RM Datasheet, PDF (274/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
12.2.2 System Options Register 2 (SIM_SOPT2)
SOPT2 contains the controls for selecting many of the module clock source options on
this device. See the Clock Distribution chapter for more information including clocking
diagrams and definitions of device clocks.
Address: SIM_SOPT2 is 4004_7000h base + 1004h offset = 4004_8004h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
SDHCSRC
I2SSRC
TIMESRC
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
FBSL
W
Reset 0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
SIM_SOPT2 field descriptions
Field
31–30
Reserved
29–28
SDHCSRC
Description
This read-only field is reserved and always has the value zero.
SDHC clock source select
Selects the clock source for the SDHC clock.
27–26
Reserved
25–24
I2SSRC
00 Core/system clock.
01 MCGPLLCLK/MCGFLLCLK clock
10 OSCERCLK clock
11 External bypass clock (SDHC0_CLKIN)
This read-only field is reserved and always has the value zero.
I2S master clock source select
Selects the clock source for I²S master clock.
00 Core/system clock divided by the I²S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC,
I2SDIV] descriptions.
01 MCGPLLCLK/MCGFLLCLK clock divided by the I²S fractional clock divider. See the
SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
274
Freescale Semiconductor, Inc.