K60P100M100SF2RM Datasheet, PDF (1120/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Register definition
RTC_WAR field descriptions (continued)
Field
1
TPRW
Time Prescaler Register Write
Description
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0
TSRW
0 Writes to the time prescaler register are ignored.
1 Writes to the time prescaler register complete as normal.
Time Seconds Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the time seconds register are ignored.
1 Writes to the time seconds register complete as normal.
43.2.10 RTC Read Access Register (RTC_RAR)
Address: RTC_RAR is 4003_D000h base + 804h offset = 4003_D804h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RTC_RAR field descriptions
Field
31–8
Reserved
7
IERR
Description
This read-only field is reserved and always has the value zero.
Interrupt Enable Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
6
LRR
0 Reads to the interrupt enable register are ignored.
1 Reads to the interrupt enable register complete as normal.
Lock Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
5
SRR
0 Reads to the lock register are ignored.
1 Reads to the lock register complete as normal.
Status Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the status register are ignored.
1 Reads to the status register complete as normal.
Table continues on the next page...
1120
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.