K60P100M100SF2RM Datasheet, PDF (1427/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

49.4.4.1 Classic SPI Transfer Format (CPHA = 0)
Chapter 49 SPI (DSPI)
The transfer format shown in following figure is used to communicate with peripheral
SPI slave devices where the first data bit is available on the first clock edge. In this
format, the master and slave sample their SIN pins on the odd-numbered SCK edges and
change the data on their SOUT pins on the even-numbered SCK edges.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCK (CPOL = 0)
SCK (CPOL = 1)
Master and Slave
Sample
Master SOUT/
Slave SIN
Master SIN/
Slave SOUT
PCSx/SS
t_CSC
MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4
MSB first (LSBFE = 1): LSB
t_{CSC =} ^PCS to SCK delay
Bit 1
Bit 2
Bit 3
t_ASC
tDT
=₌
After _{SCK delay}
Delay after Transfer
(Minimum
CS
idle
time)
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
tASC tDT _tCSC
Figure 49-94. DSPI Transfer Timing Diagram (MTFE=0, CPHA=0, FMSZ=8)
The master initiates the transfer by placing its first data bit on the SOUT pin and asserting
the appropriate peripheral chip select signals to the slave device. The slave responds by
placing its first data bit on its SOUT pin. After the tCSC delay elapses, the master outputs
the first edge of SCK. The master and slave devices use this edge to sample the first input
data bit on their serial data input signals. At the second edge of the SCK the master and
slave devices place their second data bit on their serial data output signals. For the rest of
the frame the master and the slave sample their SIN pins on the odd-numbered clock
edges and changes the data on their SOUT pins on the even-numbered clock edges. After
the last clock edge occurs a delay of t_ASC is inserted before the master negates the PCS
signals. A delay of t_DT is inserted before a new frame transfer can be initiated by the
master.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1427