K60P100M100SF2RM Datasheet, PDF (1734/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
• Bit clock — Serially clocks the data bits in and out of the I²S port. This clock is
either generated internally or taken from external clock source (through the Tx/Rx
clock ports).
• Word clock — Counts the number of data bits per word (8, 10, 12, 16, 18, 20, 22 or
24 bits). This clock is generated internally from the bit clock.
• Frame clock (frame sync) — Counts the number of words in a frame. This signal can
be generated internally from the bit clock, or taken from external source (from the
Tx/Rx frame sync ports).
• Master clock —In master mode, this is an integer multiple of frame clock. It is used
in cases when I²S has to provide the clock.
Ensure that the bit clock frequency (internally generated by dividing the network clock or
sourced from external device through Tx/Rx clock ports) is never greater than 1/5 of the
peripheral clock frequency.
In normal mode, the bit clock, used to serially clock the data, is visible on the serial
transmit clock (STCK) and serial receive clock (SRCK) ports. The word clock is an
internal clock used to determine when transmission of an 8, 10, 12, 16, 18, 20, 22 or 24
bit word has completed. The word clock then clocks the frame clock, which counts the
number of words in the frame. The frame clock can be viewed on the STFS and SRFS
frame sync ports, because a frame sync generates after the correct number of words in the
frame have passed. In master and synchronous mode, the SRCK port is used as serial
oversampling clock (network clock) enabled by the CR[SYSCLKEN] bit. This serial
system clock is an oversampling clock of the frame sync clock (STFS). In this mode, the
word length (WL), prescaler range (PSR), prescaler modulus (PM), and frame rate (DC)
selects the ratio of network clock to sampling clock, STFS. In I²S mode, the
oversampling clock network clock is available on this port if the CR[SYSCLKEN] bit is
set.
The following figure shows the relationship between the clocks and the dividers. The bit
clock can be received from an I²S clock port or can be generated from the network clock
through a divider, as shown in Figure 53-56.
Serial bit clock
Word divider
(/8, /10, /12, /16,
/18, /20, /22, /24)
Word clock
Frame divider
(/1 to /32)
Frame clock
Figure 53-55. I²S clocking
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.