K60P100M100SF2RM Datasheet, PDF (1402/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
49.3.2 DSPI Transfer Count Register (SPIx_TCR)
TCR contains a counter that indicates the number of SPI transfers made. The transfer
counter is intended to assist in queue management. Do not write the TCR when the DSPI
is in the Running state.
Addresses: SPI0_TCR is 4002_C000h base + 8h offset = 4002_C008h
SPI1_TCR is 4002_D000h base + 8h offset = 4002_D008h
SPI2_TCR is 400A_C000h base + 8h offset = 400A_C008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SPI_TCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_TCR field descriptions
Field
31–16
SPI_TCNT
15–0
Reserved
SPI Transfer Counter
Description
Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field increments every time the last
bit of a SPI frame is transmitted. A value written to SPI_TCNT presets the counter to that value.
SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT field is set in the executing SPI
command. The Transfer Counter wraps around; incrementing the counter past 65535 resets the counter
to zero.
This read-only field is reserved and always has the value zero.
49.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode)
(SPIx_CTARn)
CTAR registers are used to define different transfer attributes. The number of CTAR
registers is parameterized in the RTL and can be from two to eight registers. Do not write
to the CTAR registers while the DSPI is in the Running state.
In master mode, the CTAR registers define combinations of transfer attributes such as
frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. In
slave mode, a subset of the bitfields in CTAR0 are used to set the slave transfer attributes.
When the DSPI is configured as an SPI master, the CTAS field in the command portion
of the TX FIFO entry selects which of the CTAR register is used. When the DSPI is
configured as an SPI bus slave, the CTAR0 register is used.
1402
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.