K60P100M100SF2RM Datasheet, PDF (1075/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

41.2.1
Chapter 41 Low power timer (LPTMR)
Detailed signal descriptions
Table 41-2. LPTMR interface-detailed signal descriptions
Signal
LPTMR_ALTn
I/O
Description
I Pulse counter input.
The LPTMR can select one of the input pins to be used in pulse counter mode.
State meaning
Assertion-If configured for pulse counter mode with active
high input then assertion causes the LPTMR counter
register to increment.
Negation-If configured for pulse counter mode with active
low input then negation cause the LPTMR counter
register to increment.
Timing
Assertion or negation may occur at any time; input may
assert asynchronously to the bus clock.
41.3 Memory map and register definition
NOTE
The LPTMR registers are reset only on a POR or LVD event.
See LPTMR power and reset for more details.
Absolute
address
(hex)
LPTMR memory map
Register name
Width
(in bits)
Access
Reset value
4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR)
32
R/W 0000_0000h
4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR)
32
R/W 0000_0000h
4004_0008 Low Power Timer Compare Register (LPTMR0_CMR)
32
R/W 0000_0000h
4004_000C Low Power Timer Counter Register (LPTMR0_CNR)
32
R
0000_0000h
Section/
page
41.3.1/
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41.3.2/
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41.3.3/
1079
41.3.4/
1079
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1075