K60P100M100SF2RM Datasheet, PDF (1048/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit
is set when the second rising edge is detected, that is, the edge selected by ELS(n
+1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the period were
captured and the C(n)V and C(n+1)V registers are ready for reading.
FTM counter
channel (n) input
(after the filter
channel input)
DECAPEN bit
2
1
3
4
6
5
8
7
9
12
11
10
15
14
13
16
19
18
17
20
23
22
21
24
25
28
27
26
set DECAPEN
DECAP bit
C(n)V
set DECAP
1
3 5 6 ₇ 8 9 10 11 12 14 15 16 18 19 20 21 22 23 ₂₄ 26
CH(n)F bit
C(n+1)V
clear CH(n)F
2
CH(n+1)F bit
4
6 7 8 9 10 11 12 13 15 16 17 19 20 21 22 23 24 25 27
clear CH(n+1)F
Note
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
Figure 39-248. Dual Edge Capture – Continuous Mode to Measure of the Period Between
Two Consecutive Rising Edges
39.4.24.5 Read Coherency Mechanism
The dual edge capture mode implements a read coherency mechanism between the FTM
counter value captured in C(n)V and C(n+1)V registers. The read coherency mechanism
is illustrated in the following figure. In this example, the channels (n) and (n+1) are in
dual edge capture – continuous mode for positive polarity pulse width measurement.
Thus, the channel (n) is configured to capture the FTM counter value when there is a
rising edge at channel (n) input signal, and channel (n+1) to capture the FTM counter
value when there is a falling edge at channel (n) input signal.
1048
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.