K60P100M100SF2RM Datasheet, PDF (754/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register descriptions
31.1.2 Block diagram
This is a block diagram of the CRC.
TOT
WAS
FXOR
TOTR
CRC Data Register
[31:24]
[23:16]
[15:8]
[7:0]
CRC Polynomial
Register
[31:24]
[23:16]
[15:8]
[7:0]
Reverse
Logic
Seed
Combine
Logic
Data
Checksum
CRC Data
CRC Engine
Polynomial
NOT
Logic
Reverse
Logic
CRC Data Register
[31:24]
[23:16]
[15:8]
[7:0]
16-/32-bit Select
TCRC
Figure 31-1. Programmable cyclic redundancy check (CRC) block diagram
31.1.3 Modes of operation
Various MCU modes affect the CRC module's functionality.
31.1.3.1 Run mode
This is the basic mode of operation.
31.1.3.2 Low power modes (wait or stop)
Any CRC calculation in progress stops when the MCU enters a low power mode that
disables the module clock. It resumes after the clock is enabled or via the system reset for
exiting the low power mode. Clock gating for this module is MCU dependent.
31.2 Memory map and register descriptions
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
754
Freescale Semiconductor, Inc.