K60P100M100SF2RM Datasheet, PDF (771/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Direct loads
(commands only)
CNOP, ADRA, MVRA, MVAR, AESS, AESIS,
AESR, AESIR, DESR, DESK, HASH, SHS,
MDS, SHS2, and ILL commands
Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
0xE008_1000
Indirect load/stores
(commands & operands)
0xE008_1800
0xE008_0040
LDR CAx
STR CAx
ADR CAx
RADR CAx
0xE008_1840
0xE008_1868
0xE008_1880
0xE008_18A8
0xE008_18C0
0xE008_18E8
0xE008_1900
0xE008_1928
Reserved
(terminated with error)
XOR CAx
ROTL CAx
AESC CAx
AESIC CAx
0xE008_1980
0xE008_19A8
0xE008_19C0
0xE008_19E8
0xE008_1B00
0xE008_1B28
0xE008_1B40
0xE008_1B68
Reserved
(terminated with illegal command)
0xE008_17FF
Figure 32-15. MMCAU memory map
0xE008_1FFF
32.6.1.1 Direct Loads
The MMCAU supports writing multiple commands in each 32-bit direct write operation.
Each 9-bit opcode also includes a valid bit. Therefore, one, two, or three commands can
be transmitted in a single 32-bit PPB write. The following figure illustrates the accepted
formats for the 32-bit MMCAU write data value:
31
28
24
20
16
12
8
4
0
1
CAU_CMD1
0000000000000000000000
1 command
31
28
24
20
1
CAU_CMD1
01
16
12
CAU_CMD2
8
4
0
00000000000
2 commands
31
28
24
20
1
CAU_CMD1
01
16
12
CAU_CMD2
8
01
4
CAU_CMD3
0
3 commands
Figure 32-16. Direct loads
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
771