K60P100M100SF2RM Datasheet, PDF (766/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Features
This partitioning of functions is key to minimizing size of the MMCAU while
maintaining a high level of throughput. Using software for some functions also simplifies
the MMCAU design. The CAU implements a set of coprocessor commands that operate
on a register file of 32-bit registers.
32.4 Features
The MMCAU includes these distinctive features:
• Supports DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms
• Simple, flexible programming model
• Ability to send up to three commands in one data write operation
32.5 Memory Map/Register Definition
The CAU contains multiple registers used by each of the supported algorithms. The
following table shows which registers are applicable to each supported algorithm, and
indicates the corresponding letter designations for each algorithm. For more information
on these letter designations, refer to the algorithm specifications.
Code
0
1
2
3
4
5
6
Register
DES
CAU status
—
register (CASR)
CAU
—
accumulator
(CAA)
General
C
purpose register
0 (CA0)
General
D
purpose register
1 (CA1)
General
L
purpose register
2 (CA2)
General
R
purpose register
3 (CA3)
General
—
purpose register
4 (CA4)
AES
—
—
W0
W1
W2
W3
—
MD5
—
a
—
b
c
d
—
Table continues on the next page...
SHA-1
—
T
A
B
C
D
E
SHA-256
—
T
A
B
C
D
E
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
766
Freescale Semiconductor, Inc.