K60P100M100SF2RM Datasheet, PDF (194/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Reset
6.2.1 Power-on reset (POR)
When power is initially applied to the MCU or when the supply voltage drops below the
power-on reset re-arm voltage level (V_POR), the POR circuit causes a POR reset
condition.
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has
risen above the LVD low threshold (V_LVDL). The POR and LVD bits in SRSL register
are set following a POR.
6.2.2 System resets
Resetting the MCU provides a way to start processing from a known set of initial
conditions. System reset begins with the on-chip regulator in full regulation and system
clocking generation from an internal reference. When the processor exits reset, it
performs the following:
• Reads the start SP (SP_main) from vector-table offset 0
• Reads the start PC from vector-table offset 4
• LR is set to 0xFFFF_FFFF
The on-chip peripheral modules are disabled and the non-analog I/O pins are initially
configured as disabled. The pins with analog functions assigned to them default to their
analog function after reset.
During and following a reset, the JTAG pins have their associated input pins configured
as:
• TDI in pull-up (PU)
• TCK in pull-down (PD)
• TMS in PU
and associated output pin configured as:
• TDO with no pull-down or pull-up
Note that the nTRST signal is initially configured as disabled, however once configured
to its JTAG functionality its associated input pin is configured as:
• nTRST in PU
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
194
Freescale Semiconductor, Inc.