K60P100M100SF2RM Datasheet, PDF (419/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 20 Direct memory access multiplexer (DMAMUX)
In this mode, the DMA channel is disabled. Since disabling and enabling of DMA
channels is done primarily via the DMA configuration registers, this mode is used
mainly as the reset state for a DMA channel in the DMA channel MUX. It may also
be used to temporarily suspend a DMA channel while reconfiguration of the system
takes place (e.g. changing the period of a DMA trigger).
• Normal mode
In this mode, a DMA source (such as DSPI transmit or DSPI receive) is routed
directly to the specified DMA channel. The operation of the DMA MUX in this
mode is completely transparent to the system.
• Periodic trigger mode
In this mode, a DMA source may only request a DMA transfer (such as when a
transmit buffer becomes empty or a receive buffer becomes full) periodically.
Configuration of the period is done in the registers of the periodic interrupt timer
(PIT). This mode is only available for channels 0-3.
20.2 External signal description
The DMA MUX has no external pins.
20.3 Memory map/register definition
This section provides a detailed description of all memory-mapped registers in the DMA
MUX.
The following table shows the memory map for the DMA MUX.
All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses
must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit
boundaries. As an example, CHCFG0 through CHCFG3 are accessible by a 32-bit read/
write to address 'base + 0x00', but performing a 32-bit access to address 'base + 0x01' is
illegal.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
419