K60P100M100SF2RM Datasheet, PDF (1573/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 52 Secured digital host controller (SDHC)
SDHC memory map (continued)
Absolute
address
(hex)
Register name
400B_1030 Interrupt Status Register (SDHC_IRQSTAT)
400B_1034 Interrupt Status Enable Register (SDHC_IRQSTATEN)
400B_1038 Interrupt Signal Enable Register (SDHC_IRQSIGEN)
400B_103C Auto CMD12 Error Status Register (SDHC_AC12ERR)
400B_1040 Host Controller Capabilities (SDHC_HTCAPBLT)
400B_1044 Watermark Level Register (SDHC_WML)
400B_1050 Force Event Register (SDHC_FEVT)
400B_1054 ADMA Error Status Register (SDHC_ADMAES)
400B_1058 ADMA System Address Register (SDHC_ADSADDR)
400B_10C0 Vendor Specific Register (SDHC_VENDOR)
400B_10C4 MMC Boot Register (SDHC_MMCBOOT)
400B_10FC Host Controller Version (SDHC_HOSTVER)
Width
(in bits)
Access
Reset value
Section/
page
32
R/W
0000_0000h
52.4.13/
1595
32
R/W
117F_013Fh
52.4.14/
1601
32
R/W
0000_0000h
52.4.15/
1604
32
R
0000_0000h
52.4.16/
1606
32
R
07F3_0000h
52.4.17/
1609
32
R/W
0010_0010h
52.4.18/
1611
W
32
(always
reads
0000_0000h
52.4.19/
1611
zero)
32
R
0000_0000h
52.4.20/
1614
32
R/W
0000_0000h
52.4.21/
1616
32
R/W
0000_0001h
52.4.22/
1616
32
R/W
0000_0000h
52.4.23/
1618
32
R
0000_1201h
52.4.24/
1619
52.4.1 DMA System Address Register (SDHC_DSADDR)
This register contains the physical system memory address used for DMA transfers.
Address: SDHC_DSADDR is 400B_1000h base + 0h offset = 400B_1000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DSADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_DSADDR field descriptions
Field
31–2
DSADDR
DMA System Address
Description
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1573