K60P100M100SF2RM Datasheet, PDF (119/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
ADC Channel
(SC1n[ADCH])
11001
11010
11011
11100
11101
11110
11111
Channel
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Input signal
(SC1n[DIFF]= 1)
Reserved
Temperature Sensor (Diff)
Bandgap (Diff)⁹
Reserved
-VREFH (Diff)
Reserved
Module Disabled
Input signal
(SC1n[DIFF]= 0)
Reserved
Temperature Sensor (S.E)
Bandgap (S.E)⁹
Reserved
VREFH (S.E)
VREFL
Module Disabled
1. Interleaved with ADC1_DP3 and ADC1_DM3
2. Interleaved with ADC1_DP3
3. Interleaved with ADC1_DP0 and ADC1_DM0
4. Interleaved with ADC1_DP0
5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter
for details.
6. Interleaved with ADC1_SE8
7. Interleaved with ADC1_SE9
8. Interleaved with ADC1_DM3
9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this
ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data
sheet for the bandgap voltage (V_BG) specification.
3.7.1.4 ADC1 Connections/Channel Assignment
NOTE
As indicated in the following tables, each ADCx_DPx input
and certain ADCx_DMx inputs may operate as single-ended
ADC channels in single-ended mode.
3.7.1.4.1 ADC1 Channel Assignment for 100-Pin Package
ADC Channel
(SC1n[ADCH])
00000
00001
00010
00011
00100⁵
00101⁵
00110⁵
00111⁵
00100⁵
00101⁵
00110⁵
Channel
DAD0
DAD1
DAD2
DAD3
AD4a
AD5a
AD6a
AD7a
AD4b
AD5b
AD6b
Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
ADC1_DP0 and ADC1_DM0¹ ADC1_DP0²
ADC1_DP1 and ADC1_DM1 ADC1_DP1
PGA1_DP and PGA1_DM PGA1_DP
ADC1_DP3 and ADC1_DM3³ ADC1_DP3⁴
Reserved
ADC1_SE4a
Reserved
ADC1_SE5a
Reserved
ADC1_SE6a
Reserved
ADC1_SE7a
Reserved
ADC1_SE4b
Reserved
ADC1_SE5b
Reserved
ADC1_SE6b
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
119