K60P100M100SF2RM Datasheet, PDF (831/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 34 Analog-to-Digital Converter (ADC)
When the conversion is completed, the result is placed in the data registers associated
with the ADHWTSn received (ADHWTSA active selects RA register; ADHWTSn active
selects Rn register). The conversion complete flag associated with the ADHWTSn
received (the COCO bit in SC1n register) is then set and an interrupt is generated if the
respective conversion complete interrupt has been enabled (AIEN=1).
34.4.5 Conversion control
Conversions can be performed as determined by the CFG1[MODE] bits and the
SC1n[DIFF] bit as shown in the description of CFG1[MODE].
Conversions can be initiated by a software or hardware trigger. In addition, the ADC
module can be configured for low power operation, long sample time, continuous
conversion, hardware average, and automatic compare of the conversion result to a
software determined compare value.
34.4.5.1 Initiating conversions
A conversion is initiated:
• Following a write to SC1A register (with ADCH bits not all 1's) if software triggered
operation is selected (ADTRG=0).
• Following a hardware trigger (ADHWT) event if hardware triggered operation is
selected (ADTRG=1) and a hardware trigger select event (ADHWTSn) has occurred.
The channel and status fields selected depend on the active trigger select signal
(ADHWTSA active selects SC1A register; ADHWTSn active selects SC1n register;
if neither is active, the off condition is selected).
Note
Selecting more than one hardware trigger select signal
(ADHWTSn) prior to a conversion completion will result
in unknown results. To avoid this, select only one hardware
trigger select signal (ADHWTSn) prior to a conversion
completion.
• Following the transfer of the result to the data registers when continuous conversion
is enabled (ADCO=1).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
831