K60P100M100SF2RM Datasheet, PDF (1404/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
SPIx_CTARn field descriptions (continued)
Field
30–27
FMSZ
26
CPOL
Frame Size
Description
The number of bits transferred per frame is equal to the FMSZ field value plus 1. The minimum valid
FMSZ field value is 3.
Clock Polarity
Selects the inactive state of the Serial Communications Clock (SCK). This bit is used in both master and
slave mode. For successful communication between serial devices, the devices must have identical clock
polarities. When the Continuous Selection Format is selected, switching between clock polarities without
stopping the DSPI can cause errors in the transfer due to the peripheral device interpreting the switch of
clock polarity as a valid clock edge.
25
CPHA
0 The inactive state value of SCK is low.
1 The inactive state value of SCK is high.
Clock Phase
Selects which edge of SCK causes data to change and which edge causes data to be captured. This bit is
used in both master and slave mode. For successful communication between serial devices, the devices
must have identical clock phase settings. In Continuous SCK mode, the bit value is ignored and the
transfers are done as if the CPHA bit is set to 1.
24
LSBFE
0 Data is captured on the leading edge of SCK and changed on the following edge.
1 Data is changed on the leading edge of SCK and captured on the following edge.
LBS First
Specifies whether the LSB or MSB of the frame is transferred first.
23–22
PCSSCK
21–20
PASC
19–18
PDT
0 Data is transferred MSB first.
1 Data is transferred LSB first.
PCS to SCK Delay Prescaler
Selects the prescaler value for the delay between assertion of PCS and the first edge of the SCK. See the
CSSCK field description for information on how to compute the PCS to SCK Delay. Refer PCS to SCK
Delay (t_CSC) for more details.
00 PCS to SCK Prescaler value is 1.
01 PCS to SCK Prescaler value is 3.
10 PCS to SCK Prescaler value is 5.
11 PCS to SCK Prescaler value is 7.
After SCK Delay Prescaler
Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS. See the
ASC field description for information on how to compute the After SCK Delay.Refer After SCK Delay
(t_ASC) for more details.
00 Delay after Transfer Prescaler value is 1.
01 Delay after Transfer Prescaler value is 3.
10 Delay after Transfer Prescaler value is 5.
11 Delay after Transfer Prescaler value is 7.
Delay after Transfer Prescaler
Table continues on the next page...
1404
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.