K60P100M100SF2RM Datasheet, PDF (458/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
21.3.7 Clear Enable Request Register (DMA_CERQ)
The CERQ provides a simple memory-mapped mechanism to clear a given bit in the
ERQ to disable the DMA request for a given channel. The data value on a register write
causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a
global clear function, forcing the entire contents of the ERQ to be cleared, disabling all
DMA request inputs. If NOP is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: DMA_CERQ is 4000_8000h base + 1Ah offset = 4000_801Ah
Bit
7
6
5
4
3
2
1
0
Read
0
0
0
Write
NOP
CAER
0
CERQ
Reset
0
0
0
0
0
0
0
0
DMA_CERQ field descriptions
Field
7
NOP
6
CAER
5–4
Reserved
3–0
CERQ
Description
0 Normal operation
1 No operation, ignore the other bits in this register
Clear All Enable Requests
0 Clear only the ERQ bit specified in the CERQ field
1 Clear all bits in ERQ
This field is reserved.
Clear Enable Request
Clears the corresponding bit in ERQ
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
458
Freescale Semiconductor, Inc.