K60P100M100SF2RM Datasheet, PDF (422/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
such, the configuration of the periodic triggering interval is done via configuration
registers in the PIT. Please refer to Periodic Interrupt Timer chapter for more information
on this topic.
Note
Because of the dynamic nature of the system (i.e. DMA channel
priorities, bus arbitration, interrupt service routine lengths, etc.),
the number of clock cycles between a trigger and the actual
DMA transfer cannot be guaranteed.
Source #1
Source #2
Source #3
Trigger #1
Trigger #2
DMA Channel #0
DMA Channel #1
Source #x
Always #1
Trigger #4
DMA Channel #3
Always #y
Figure 20-19. DMA MUX triggered channels
The DMA channel triggering capability allows the system to "schedule" regular DMA
transfers, usually on the transmit side of certain peripherals, without the intervention of
the processor. This trigger works by gating the request from the peripheral to the DMA
until a trigger event has been seen. This is illustrated in the following figure.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
422
Freescale Semiconductor, Inc.