K60P100M100SF2RM Datasheet, PDF (1628/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
starts, which is 31 bytes, more than 6 words. The host driver writer may take this variable
burst length into account. It is also acceptable to configure the burst length as the divisor
of the block size, so that each time the burst length will be the same.
52.5.2.3 Crossbar switch master interface
It is possible that the internal DMA engine could fail during the data transfer. When this
error occurs, the DMA engine stops the transfer and goes to the idle state as well as the
internal data buffer stops accepting incoming data. The IRQSTAT[DMAE] is set to
inform the driver.
Once the DMAE interrupt is received, the software shall send a CMD12 to abort the
current transfer and read the DSADDR[DSADDR] to get the starting address of the
corrupted block. After the DMA error is fixed, the software should apply a data reset and
re-start the transfer from this address to recover the corrupted block.
52.5.2.4 ADMA engine
In the SD host controller standard, the new DMA transfer algorithm called the ADMA
(advanced DMA) is defined. For simple DMA, once the page boundary is reached, a
DMA interrupt will be generated and the new system address shall be programmed by the
host driver. The ADMA defines the programmable descriptor table in the system
memory. The host driver can calculate the system address at the page boundary and
program the descriptor table before executing ADMA. It reduces the frequency of
interrupts to the host system. Therefore, higher speed DMA transfers could be realized
since the host MCU intervention would not be needed during long DMA based data
transfers.
There are two types of ADMA: ADMA1 and ADMA2 in host controller. ADMA1 can
support data transfer of 4 KB aligned data in system memory. ADMA2 improves the
restriction so that data of any location and any size can be transferred in system memory.
Their formats of descriptor table are different.
ADMA can recognize all kinds of descriptors define in SD host controller standard, and
if 'end' flag is detected in the descriptor, ADMA will stop after this descriptor is
processed.
52.5.2.4.1 ADMA concept and descriptor format
For ADMA1, including the following descriptors:
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.