K60P100M100SF2RM Datasheet, PDF (151/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

3.9.4.1 SPI Modules Configuration
This device contains three SPI modules.
Chapter 3 Chip Configuration
3.9.4.2 SPI clocking
The SPI module is clocked by the internal bus clock (the DSPI refers to it as system
clock). The module has an internal divider, with a minimum divide is two. So, the SPI
can run at a maximum frequency of bus clock/2.
3.9.4.3 Number of CTARs
SPI CTAR registers define different transfer attribute configurations. The SPI module
supports up to eight CTAR registers. This device supports two CTARs on all instances of
the SPI.
In master mode, the CTAR registers define combinations of transfer attributes, such as
frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In
slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer
attributes.
3.9.4.4
TX FIFO size
Table 3-68. SPI transmit FIFO size
SPI Module
SPI0
SPI1
SPI2
Transmit FIFO size
4
4
4
3.9.4.5 RX FIFO Size
SPI supports up to 16-bit frame size during reception.
Table 3-69. SPI receive FIFO size
SPI Module
SPI0
SPI1
SPI2
Receive FIFO size
4
4
4
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
151