K60P100M100SF2RM Datasheet, PDF (1100/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
Bus
Clock
(MHz)
8
8
8
8
MSC[CMTDIV]
00
01
10
11
Table 42-17. Clock Divider
Carrier Generator
Resolution (μs)
0.125
0.25
0.5
1.0
Min. Carrier
Generator Period
(μs)
0.25
0.5
1.0
2.0
Min.
Modulator Period
(μs)
1.0
2.0
4.0
8.0
The possible duty cycle options depend upon the number of counts required to complete
the carrier period. For example, 1.6 MHz signal has a period of 625 ns and will therefore
require 5 x 125 ns counts to generate. These counts may be split between high and low
times, so the duty cycles available will be 20% (one high, four low), 40% (two high, three
low), 60% (three high, two low) and 80% (four high, one low).
For lower frequency signals with larger periods, higher resolution (as a percentage of the
total period) duty cycles are possible.
The carrier signal is generated by counting a register-selected number of input clocks
(125 ns for an 8 MHz bus) for both the carrier high time and the carrier low time. The
period is determined by the total number of clocks counted. The duty cycle is determined
by the ratio of high time clocks to total clocks counted. The high and low time values are
user programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the
generation of dual frequency FSK (frequency shift keying) protocols without CPU
intervention.
Note
Only non-zero data values are allowed. The carrier generator
will not work if any of the count values are equal to zero.
MSC[MCGEN] bit must be set and MSC[BASE] bit must be cleared to enable carrier
generator clocks. When MSC[BASE] bit is set, the carrier output to the modulator is held
high continuously. Following figure represents the block diagram of the clock generator.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.