K60P100M100SF2RM Datasheet, PDF (1392/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
49.1.3.1 SPI Configuration
The SPI configuration allows the DSPI to send and receive serial data. This configuration
allows the DSPI to operate as a basic SPI block with internal FIFOs supporting external
queues operation. Transmit data and received data reside in separate FIFOs. The host
CPU or a DMA controller read the received data from the receive FIFO and write
transmit data to the transmit FIFO.
For queued operations the SPI queues can reside in system RAM, external to the DSPI.
Data transfers between the queues and the DSPI FIFOs are accomplished by a DMA
controller or host CPU. The following figure shows a system example with DMA, DSPI
and external queues in system RAM.
System RAM
Addr/Ctrl
Done
RX Queue
TX Queue
Data
Data ^{DMA Controller}
Data
DSPI
Data
Addr/Ctrl
Req
TX FIFO RX FIFO
Shift Register
Figure 49-2. DSPI with Queues and DMA
49.1.4 Modes of Operation
The DSPI supports the following modes of operation that can be divided into two
categories;
• Module-specific modes:
• Master mode
• Slave mode
• Module disable mode
• MCU-specific modes:
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.