K60P100M100SF2RM Datasheet, PDF (1655/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 52 Secured digital host controller (SDHC)
52.6.3.4 ADMA usage
To use the ADMA in a data transfer, the host driver must prepare the correct descriptor
chain prior to sending the read/write command. The steps to accomplish this are:
1. Create a descriptor to set the data length that the current descriptor group is about to
transfer. The data length should be even numbers of the block size.
2. Create another descriptor to transfer the data from the address setting in this
descriptor. The data address must be at a page boundary (4 KB address aligned).
3. If necessary, create a link descriptor containing the address of the next descriptor.
The descriptor group is created in steps 1 ~ 3.
4. Repeat steps 1 ~ 3 until all descriptors are created.
5. In the last descriptor, set the end flag to 1 and make sure the total length of all
descriptors match the product of the block size and block number configured in the
BLKATTR register.
6. Set the DSADDR register to the address of the first descriptor and set the
PROCTL[DMAS] field to 01 to select the ADMA.
7. Issue a write or read command with the XFERTYP[DMAEN] bit set to 1.
Steps 1 ~ 5 are independent of step 6, so step 6 can finish before steps 1 ~ 5. Regarding
the descriptor configuration, it is recommended not to use the link descriptor as it
requires extra system memory access.
52.6.3.5 Transfer error
This section discusses the handling of transfer errors.
52.6.3.5.1 CRC error
It is possible at the end of a block transfer, that a write CRC status error or read CRC
error occurs. For this type of error the latest block received shall be discarded. This is
because the integrity of the data block is not guaranteed. It is recommended to discard the
following data blocks and re-transfer the block from the corrupted one. For a multi-block
transfer, the host driver shall issue a CMD12 to abort the current process and start the
transfer by a new data command. In this scenario, even when the XFERTYP[AC12EN]
and BCEND bits are set, the SDHC does not automatically send a CMD12 because the
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1655