K60P100M100SF2RM Datasheet, PDF (1089/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 42 Carrier Modulator Transmitter (CMT)
42.5 CMT External Signal Descriptions
This table shows the description of the external signal.
Table 42-2. CMT Signal Descriptions
Signal
Description
I/O
CMT_IRO
Infrared Output
O
42.5.1 CMT_IRO — Infrared Output
This output signal is driven by the modulator output when MSC[MCGEN] is set and
OC[IROPEN] is set. The CMT_IRO signal starts a valid transmission with a delay, after
MSC[MCGEN] bit be asserted to high, that can be calculated based on two register bits.
The following table shows how to calculate this delay.
If MSC[MCGEN] bit is cleared and OC[IROPEN] bit is set, the signal is driven by
OC[IROL] bit. This enables user software to directly control the state of the CMT_IRO
signal by writing to OC[IROL] bit. If OC[IROPEN] bit is cleared, the signal is disabled
and is not driven by the CMT module. Therefore, CMT can be configured as a modulo
timer for generating periodic interrupts without causing signal activity.
Table 42-3. CMT_IRO signal delay calculation
Condition
MSC[CMTDIV] = 0
MSC[CMTDIV] > 0
Delay (bus clock cycles)
PPS[PPSDIV] + 2
(PPS{PPSDIV] × 2) + 3
42.6 Memory Map/Register Definition
The following registers control and monitor CMT operation.
The address of a register is the sum of a base address and an address offset. The base
address is defined at the chip level. The address offset is defined at the module level.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1089