K60P100M100SF2RM Datasheet, PDF (839/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 34 Analog-to-Digital Converter (ADC)
With the ADC range enable bit set, ACREN =1, and if compare value register 1 (CV1
value) is less than or equal to the compare value register 2 (CV2 value), then setting
ACFGT will select a trigger-if-inside-compare-range inclusive-of-endpoints function.
Clearing ACFGT will select a trigger-if-outside-compare-range, not-inclusive-of-
endpoints function.
If CV1 is greater than CV2, setting ACFGT will select a trigger-if-outside-compare-
range, inclusive-of-endpoints function. Clearing ACFGT will select a trigger-if-inside-
compare-range, not-inclusive-of-endpoints function.
If the condition selected evaluates true, COCO is set.
Upon completion of a conversion while the compare function is enabled, if the compare
condition is not true, COCO is not set and the conversion result data will not be
transferred to the result register. If the hardware averaging function is enabled, the
compare function compares the averaged result to the compare values. The same compare
function definitions apply. An ADC interrupt is generated upon the setting of COCO if
the respective ADC interrupt is enabled (AIEN=1).
Note
The compare function can monitor the voltage on a channel
while the MCU is in Wait or Normal Stop modes. The ADC
interrupt wakes the MCU when the compare condition is met.
34.4.7 Calibration function
The ADC contains a self-calibration function that is required to achieve the specified
accuracy. Calibration must be run, or valid calibration values written, after any reset and
before a conversion is initiated. The calibration function sets the offset calibration value,
the minus-side calibration values, and the plus-side calibration values. The offset
calibration value is automatically stored in the ADC offset correction register (OFS), and
the plus-side and minus-side calibration values are automatically stored in the ADC plus-
side and minus-side calibration (CLPx and CLMx) registers. The user must configure the
ADC correctly prior to calibration, and must generate the plus-side and minus-side gain
calibration results and store them in the ADC plus-side gain register (PG) after the
calibration function completes.
Prior to calibration, the user must configure the ADC's clock source and frequency, low
power configuration, voltage reference selection, sample time, and high speed
configuration according to the application's clock source availability and needs. If the
application uses the ADC in a wide variety of configurations, the configuration for which
the highest accuracy is required should be selected, or multiple calibrations can be done
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
839