K60P100M100SF2RM Datasheet, PDF (1468/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
have the ability to generate the not acknowledge after the transfer of each byte and before
the completion of the transaction. This requirement is important because SMBus does not
provide any other resend signaling. This difference in the use of the NACK signaling has
implications on the specific implementation of the SMBus port, especially in devices that
handle critical system data such as the SMBus host and the SBS components.
NOTE
In the last byte of master receive slave transmit mode, the
master must send a NACK to the bus, so FACK must be
switched off before the last byte transmits.
50.4.5 Resets
The I2C module is disabled after a reset. The I2C module cannot cause a core reset.
50.4.6 Interrupts
The I2C module generates an interrupt when any of the events in the following table
occur, provided that the IICIE bit is set. The interrupt is driven by the IICIF bit (of the
I2C Status Register) and masked with the IICIE bit (of the I2C Control Register 1). The
IICIF bit must be cleared (by software) by writing 1 to it in the interrupt routine. The
SMBus timeouts interrupt is driven by SLTF and masked with the IICIE bit. The SLTF
bit must be cleared by software by writing 1 to it in the interrupt routine. You can
determine the interrupt type by reading the Status Register.
NOTE
In master receive mode, the FACK bit must be set to zero
before the last byte transfer.
Table 50-44. Interrupt Summary
Interrupt Source
Complete 1-byte transfer
Match of received calling address
Arbitration lost
SMBus SCL low timeout interrupt flag
SMBus SCL high SDA low timeout interrupt flag
Wakeup from stop interrupt
Status
TCF
IAAS
ARBL
SLTF
SHTF2
IAAS
Flag
IICIF
IICIF
IICIF
IICIF
IICIF
IICIF
Local Enable
IICIE
IICIE
IICIE
IICIE
IICIE & SHTF2IE
IICIE & WUEN
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.