K60P100M100SF2RM Datasheet, PDF (1366/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
Suppose, for example, that the FIFO is disabled, IRMQ is enabled and there are two MBs
with the same ID, and FlexCAN starts receiving messages with that ID. Let us say that
these MBs are the second and the fifth in the array. When the first message arrives, the
matching algorithm will find the first match in MB number 2. The code of this MB is
EMPTY, so the message is stored there. When the second message arrives, the matching
algorithm will find MB number 2 again, but it is not "free-to-receive", so it will keep
looking and find MB number 5 and store the message there. If yet another message with
the same ID arrives, the matching algorithm finds out that there are no matching MBs
that are "free-to-receive", so it decides to overwrite the last matched MB, which is
number 5. In doing so, it sets the CODE field of the MB to indicate OVERRUN.
The ability to match the same ID in more than one MB can be exploited to implement a
reception queue (in addition to the full featured FIFO) to allow more time for the CPU to
service the MBs. By programming more than one MB with the same ID, received
messages will be queued into the MBs. The CPU can examine the Time Stamp field of
the MBs to determine the order in which the messages arrived.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN
supports individual masking per MB. Refer to the description of the Rx Individual Mask
Registers (RXIMRx). During the matching algorithm, if a mask bit is asserted, then the
corresponding ID bit is compared. If the mask bit is negated, the corresponding ID bit is
"don't care". Please note that the Individual Mask Registers are implemented in RAM, so
they are not initialized out of reset. Also, they can only be programmed while the module
is in Freeze Mode; otherwise, they are blocked by hardware.
FlexCAN also supports an alternate masking scheme with only four mask registers
(RGXMASK, RX14MASK, RX15MASK and RXFGMASK) for backwards
compatibility. This alternate masking scheme is enabled when the IRMQ bit in the MCR
Register is negated.
48.4.5 Move Process
There are two types of move process: move-in and move-out.
48.4.5.1 Move-in
The move-in process is the copy of a message received by an Rx SMB to a Rx Mailbox
or FIFO that has matched it. If the move destination is the Rx FIFO, attributes of the
message are also copied to the RXFIR FIFO. Each Rx SMB has its own move-in process,
1366
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.