K60P100M100SF2RM Datasheet, PDF (1610/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_HTCAPBLT field descriptions (continued)
Field
23
SRS
Suspend/Resume Support
Description
This bit indicates whether the SDHC supports suspend / resume functionality. If this bit is 0, the suspend
and resume mechanism, as well as the read Wwait, are not supported, and the host driver shall not issue
either suspend or resume commands.
22
DMAS
0b Not supported
1b Supported
DMA Support
This bit indicates whether the SDHC is capable of using the internal DMA to transfer data between system
memory and the data buffer directly.
21
HSS
0b DMA not supported
1b DMA supported
High Speed Support
This bit indicates whether the SDHC supports high speed mode and the host system can supply a SD
Clock frequency from 25 MHz to 50 MHz.
20
ADMAS
0b High speed not supported
1b High speed supported
ADMA Support
This bit indicates whether the SDHC supports the ADMA feature.
19
Reserved
18–16
MBL
0b Advanced DMA not supported
1b Advanced DMA supported
This read-only field is reserved and always has the value zero.
Max Block Length
This value indicates the maximum block size that the host driver can read and write to the buffer in the
SDHC. The buffer shall transfer block size without wait cycles.
15–0
Reserved
000b
001b
010b
011b
512 bytes
1024 bytes
2048 bytes
4096 bytes
This read-only field is reserved and always has the value zero.
1610
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.