K60P100M100SF2RM Datasheet, PDF (40/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
44.3.17 Descriptor Group Lower Address Register (ENET_GALR).......................................................................1155
44.3.18 Transmit FIFO Watermark Register (ENET_TFWR).................................................................................1155
44.3.19 Receive Descriptor Ring Start Register (ENET_RDSR).............................................................................1156
44.3.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR)................................................................1157
44.3.21 Maximum Receive Buffer Size Register (ENET_MRBR)..........................................................................1157
44.3.22 Receive FIFO Section Full Threshold (ENET_RSFL)................................................................................1158
44.3.23 Receive FIFO Section Empty Threshold (ENET_RSEM)..........................................................................1158
44.3.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)..........................................................................1159
44.3.25 Receive FIFO Almost Full Threshold (ENET_RAFL)................................................................................1159
44.3.26 Transmit FIFO Section Empty Threshold (ENET_TSEM).........................................................................1160
44.3.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM).........................................................................1160
44.3.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)..............................................................................1161
44.3.29 Transmit Inter-Packet Gap (ENET_TIPG)..................................................................................................1161
44.3.30 Frame Truncation Length (ENET_FTRL)...................................................................................................1162
44.3.31 Transmit Accelerator Function Configuration (ENET_TACC)..................................................................1162
44.3.32 Receive Accelerator Function Configuration (ENET_RACC)....................................................................1163
44.3.33 Timer Control Register (ENET_ATCR)......................................................................................................1165
44.3.34 Timer Value Register (ENET_ATVR)........................................................................................................1166
44.3.35 Timer Offset Register (ENET_ATOFF)......................................................................................................1167
44.3.36 Timer Period Register (ENET_ATPER)......................................................................................................1167
44.3.37 Timer Correction Register (ENET_ATCOR)..............................................................................................1168
44.3.38 Time-Stamping Clock Period Register (ENET_ATINC)............................................................................1168
44.3.39 Timestamp of Last Transmitted Frame (ENET_ATSTMP)........................................................................1169
44.3.40 Timer Global Status Register (ENET_TGSR).............................................................................................1169
44.3.41 Timer Control Status Register (ENET_TCSRn)..........................................................................................1170
44.3.42 Timer Compare Capture Register (ENET_TCCRn)....................................................................................1171
44.3.43 Statistic Event Counters...............................................................................................................................1172
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
40
Freescale Semiconductor, Inc.