K60P100M100SF2RM Datasheet, PDF (203/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 7
Power Management
7.1 Introduction
This chapter describes the various chip power modes and functionality of the individual
modules in these modes.
7.2 Power modes
The power management controller (PMC) provides multiple power options to allow the
user to optimize power consumption for the level of functionality needed.
Depending on the stop requirements of the user application, a variety of stop modes are
available that provide state retention, partial power down or full power down of certain
logic and/or memory. I/O states are held in all modes of operation. The following table
compares the various power modes available.
For each run mode there is a corresponding wait and stop mode. Wait modes are similar
to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode.
The very low power run (VLPR) operating mode can drastically reduce runtime power
when the maximum bus frequency is not required to handle the application needs.
The three primary modes of operation are run, wait and stop. The WFI instruction
invokes both wait and stop modes for the chip. The primary modes are augmented in a
number of ways to provide lower power based on application needs.
Chip mode
Table 7-1. Chip power modes
Description
Core mode
Normal run Allows maximum performance of chip. Default mode out of reset; on-
Run
chip voltage regulator is on.
Table continues on the next page...
Normal
recovery
method
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
203