K60P100M100SF2RM Datasheet, PDF (204/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Power modes
Chip mode
Table 7-1. Chip power modes (continued)
Description
Normal Wait -
via WFI
Allows peripherals to function while the core is in sleep mode,
reducing power. NVIC remains sensitive to interrupts; peripherals
continue to be clocked.
Normal Stop -
via WFI
Places chip in static state. Lowest power mode that retains all
registers while maintaining LVD protection. NVIC is disabled; AWIC is
used to wake up from interrupt; peripheral clocks are stopped.
VLPR (Very
Low Power
Run)
On-chip voltage regulator is in a low power mode that supplies only
enough power to run the chip at a reduced frequency. Reduced
frequency Flash access mode (1 MHz); LVD off; internal oscillator
provides a low power 2 MHz source for the core, the bus and the
peripheral clocks.
VLPW (Very
Low Power
Wait) -via WFI
Same as VLPR but with the core in sleep mode to further reduce
power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency.
VLPS (Very
Low Power
Stop)-via WFI
Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional. Peripheral clocks are stopped,
but LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled
(FCLK = OFF); AWIC is used to wake up from interrupt. On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency. All SRAM is operating
(content retained and I/O states held).
LLS (Low State retention power mode. Most peripherals are in state retention
Leakage Stop) mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI,
DAC can be used. NVIC is disabled; LLWU is used to wake up.
VLLS3 (Very
Low Leakage
Stop3)
VLLS2 (Very
Low Leakage
Stop2)
VLLS1 (Very
Low Leakage
Stop1)
NOTE: The LLWU interrupt must not be masked by the interrupt
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
All SRAM is operating (content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
Table continues on the next page...
Core mode
Sleep
Normal
recovery
method
Interrupt
Sleep Deep
Interrupt
Run
Interrupt
Sleep
Interrupt
Sleep Deep
Interrupt
Sleep Deep
Wakeup
Interrupt¹
Sleep Deep Wakeup Reset²
Sleep Deep Wakeup Reset²
Sleep Deep Wakeup Reset²
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
204
Freescale Semiconductor, Inc.