K60P100M100SF2RM Datasheet, PDF (1512/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and registers
51.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)
This register provides the ability to set a programmable threshold for notification of
needing additional transmit data. This register may be read at any time but should only be
written when C2[TE] is not set. Changing the value of the watermark will not clear the
S1[TDRE] flag.
Addresses: UART0_TWFIFO is 4006_A000h base + 13h offset = 4006_A013h
UART1_TWFIFO is 4006_B000h base + 13h offset = 4006_B013h
UART2_TWFIFO is 4006_C000h base + 13h offset = 4006_C013h
UART3_TWFIFO is 4006_D000h base + 13h offset = 4006_D013h
UART4_TWFIFO is 400E_A000h base + 13h offset = 400E_A013h
Bit
7
6
5
4
3
2
1
0
Read
Write
TXWATER
Reset
0
0
0
0
0
0
0
0
UARTx_TWFIFO field descriptions
Field
7–0
TXWATER
Transmit Watermark
Description
When the number of datawords in the transmit FIFO/buffer is equal to or less than the value in this
register field then an interrupt via S1[TDRE] or a DMA request via C5[TDMAS] will be generated as
determined by C5[TDMAS] and C2[TIE] fields. For proper operation the value in the TXWATER field must
be set to be less than the size of the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and
PFIFO[TXFE].
51.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)
This is a read only register that indicates how many datawords are currently in the
transmit buffer/FIFO. It may be read at anytime.
Addresses: UART0_TCFIFO is 4006_A000h base + 14h offset = 4006_A014h
UART1_TCFIFO is 4006_B000h base + 14h offset = 4006_B014h
UART2_TCFIFO is 4006_C000h base + 14h offset = 4006_C014h
UART3_TCFIFO is 4006_D000h base + 14h offset = 4006_D014h
UART4_TCFIFO is 400E_A000h base + 14h offset = 400E_A014h
Bit
7
6
5
4
3
2
1
0
Read
TXCOUNT
Write
Reset
0
0
0
0
0
0
0
0
1512
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.