K60P100M100SF2RM Datasheet, PDF (72/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Core modules
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at http://
www.arm.com.
Interrupts
Module
PPB
Nested Vectored
Interrupt Controller
Module
(NVIC)
Module
Figure 3-2. NVIC configuration
Topic
Full description
System memory map
Clocking
Power management
Private Peripheral Bus
(PPB)
Table 3-2. Reference links to related information
Related module
Nested Vectored
Interrupt Controller
(NVIC)
ARM Cortex-M4 core
Reference
http://www.arm.com
System memory map
Clock distribution
Power management
ARM Cortex-M4 core
3.2.2.1 Interrupt priority levels
This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source
in the IPR registers contains 4 bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ3
W
0000
IRQ2
0000
IRQ1
0000
IRQ0
0000
3.2.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to
generate the non-maskable interrupt request.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
72
Freescale Semiconductor, Inc.