K60P100M100SF2RM Datasheet, PDF (795/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Reset
Hardware
Software
Chapter 33 Random Number Generator (RNGB)
Table 33-8. Reset Summary
Source
ipg_hard_async_reset_b
RNG_CMD[SR]
Characteristics
Active-low,
asynchronous,
minimum 1-cycle
Active-high
Internally resets:
All interface registers
and puts RNGB into
the IDLE state
All interface registers
and puts RNGB into
the IDLE state
Affect on External
Signal:
—
—
33.4.3.1 Power-on/Hardware Reset
Asserting the ipg_hard_async_reset_b signal sets all interface registers to their default
state and puts the state machine into the IDLE mode.
33.4.3.2 Software Reset
The software reset is functionally equivalent to the hardware reset, but allows the RNGB
to be fully reset by writing to the SW_RST bit (bit-6) in the RNGB Command Register.
This bit is self-resetting. A software reset may be performed at any time.
33.4.4 RNG Interrupts
There is a single RNG interrupt generated to the processor's interrupt controller. The
source of the interrupt is determined by reading the RNG status register. If an error is the
cause of the interrupt, further information is available by reading the RNG error status
register. The interrupts can be masked by the RNG_CR[MASKDONE or MASKERR]
bits
It is strongly recommended that the error interrupt is only masked while debugging, since
masking the error interrupt could hide potentially fatal errors or conditions that could
result in corrupted results. All errors are considered fatal, requiring the RNG to be reset.
The RNG does not service any random data until a reset occurs.
The available interrupt sources are described in the following table.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
795