K60P100M100SF2RM Datasheet, PDF (1593/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
25
RSTC
24
RSTA
23–20
Reserved
19–16
DTOCV
15–8
SDCLKFS
Chapter 52 Secured digital host controller (SDHC)
SDHC_SYSCTL field descriptions (continued)
Description
• Buffer Write Enable
• Read Transfer Active
• Write Transfer Active
• DAT Line Active
• Command Inhibit (DAT) Protocol Control register
• Continue Request
• Stop At Block Gap Request Interrupt Status register
• Buffer Read Ready
• Buffer Write Ready
• DMA Interrupt
• Block Gap Event
• Transfer Complete
0b No reset
1b Reset
Software Reset For CMD Line
Only part of the command circuit is reset.
The following registers and bits are cleared by this bit:
• PRSSTAT[CIHB]
• IRQSTAT[CC]
0b No reset
1b Reset
Software Reset For ALL
This reset effects the entire host controller except for the card detection circuit. Register bits of type ROC,
RW, RW1C, RWAC are cleared. During its initialization, the host driver shall set this bit to 1 to reset the
SDHC. The SDHC shall reset this bit to 0 when the capabilities registers are valid and the host driver can
read them. Additional use of software reset for all does not affect the value of the capabilities registers.
After this bit is set, it is recommended that the host driver reset the external card and re-initialize it.
0b No reset
1b Reset
This read-only field is reserved and always has the value zero.
Data Timeout Counter Value
This value determines the interval by which DAT line timeouts are detected. Refer to the IRQSTAT[DTOE]
for information on factors that dictate time-out generation. Time-out clock frequency will be generated by
dividing the base clock SDCLK value by this value.
The host driver can clear the IRQSTATEN[DTOESEN] to prevent inadvertent time-out events.
0000b
0001b
...
1110b
1111b
SDCLK x 2¹³
SDCLK x 2¹⁴
SDCLK x 2²⁷
Reserved
SDCLK Frequency Select
This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly,
rather this register holds the prescaler (this register) and divisor (next register) of the base clock
frequency register.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1593